6809 INSTRUCTION SET

The instruction set of the MC6809E is similar to that of the MC6800 and is upward compatible at the source code level. The number of opcodes has been reduced from 72 to 59, but because of the expanded architecture and additional addressing modes, the number of available opcodes (with different addressing modes) has risen from 197 to 1464.
Some of the new instructions are described in detail below.

PSHU/PSHS

The push instructions have the capability of pushing onto either the hardware stack (S) or user stack (U) any single register or set of registers with a single instruction.

PULU/PULS

The pull instructions have the same capability of the push instruction, in reverse order. The byte immediately following the push or pull opcode determines which register or registers are to be pushed or pulled. The actual push/pull sequence is fixed; each bit defines a unique register to push or pull, as shown below.

TFR/EXG

Within the MC6809E, any register may be transferred to or exchanged with another of like size; i.e. 8-bit to 8-bit or 16-bit to 16-bit.
Bits 4-7 of postbyte define the source register, while bits 0-3 represent the destination register. These are denoted as follows:

LEAX/LEAY/LEAU/LEAS

The LEA (Load Effective Address) works by calculating the effective address used in an indexed instruction and stores that address value, rather than the data at that address, in a pointer register. This makes all the features of the internal addressing hardware available to the programmer. Some of the implications of this instruction are illustrated in Table 3

The LEA instruction also allows the user to access data and tables in a position independent manner. For example:

LEAX MSG1, PCR
LBSR PDATA			(Print message routine)
MSG1 FCC 'MESSAGE'

This sample program prints 'MESSAGE'. By writing MSG1, PCR, the assembler computes the distance between the present address and MSG1. This result is placed as a constant into the LEAX instruction which will be indexed from the PC value at the time of execution. No matter where the code is located when it is executed, the computed offset from the PC will put the absolute address of MSG1 into the X pointer register. This code is totally position-independent.

The LEA instructions are very powerful and use an internal holding register (temp). Care must be exercised when using the LEA instructions with the auto increment and auto decrement addressing modes due to the sequence of internal operations. The LEA internal sequence is outlined as follows:

LEAa,b+ (any of the 18 bit pointer registers X, Y, U, or S may be substituted for a and b.)

1. b    => temp		(calculate the EA)
2. b+1  => b 		(modify b, postincrement)
3. temp => a		(load a)

LEAa, - b

1. b-1  => temp		(calculate EA with predecrement)
2. b-1  => b		(modify b, predecrement)
3. temp => a		(load a)

TABLE 3 - LEA EXAMPLES

Auto increment-by-two and auto decrement-by-two instructions work similarly. Note that LEAX,X+ does not change X; however LEAX, - X does decrement X. LEAX 1,X should be used to increment X by one.

MUL

Multiplies the unsigned binary numbers in the A and B accumulator and places the unsigned result into the 16-bit D accumulator. This unsigned multiply also allows multiple-precision muitiplications.

LONG AND SHORT RELATIVE BRANCHES

The MC6809E has the capability of program-counter relative branching throughout the entire memory map. In this mode, if the branch is to be taken, the 8- or 16-bit signed offset is added to the value of the program counter to be used as the effective address. This allows the program to branch anywhere in the 64K memory map. Position independent code can be easily generated through the use of relative branching. Both short (8 bit) and long (16 bit) branches are available

SYNC

After encountering a sync instruction, the MPU enters a sync state, stops processing instructions, and waits for an interrupt. If the pending interrupt is non-maskable (!NMI) l or maskable (!FIRQ, !IRQ) with its mask bit (F or l) clear, the processor will cear the sync state and perform the normal interrupt stacking and service routine. Since !FIRQ and !IRQ are not edge triggered, a low level with a minimum duration of three bus cydes is required to assure that the interrupt will be taken. If the pending interrupt is maskable (!FIRQ, !IRQ) with its mask bit (F or I) set, the processor will clear the sync state and continue processing by executing the next in-line instruction. Figure 16 depicts sync timing.

SOFTWARE INTERRUPTS

A software interrupt is an instruction which will cause an interrupt and its associated vector fetch. These software interrupts are useful in operating system calls, software debugging, trace operations, memory mapping, and software development systems. Three levels of SWI are available on the MC6809E and are prioritized in the following order: SWI, SWI2, SWI3.

16-BIT OPERATION

The MC6809 has the capability of processing 16-bit data. Thee instructions include loads. stores, compares, adds, subtracts, transfers. exchanges, pushes, and pulls.

CYCLE-BY-CYCLE OPERATION

The address-bus cycle-by-cycle performance chart (Figure 16) illustrates the memory-access sequence corresponding to each possible instruction and addressing mode in the MC6809E. Each instruction begins with an opcode fetch. While that opcode is being internally decoded. the next program byte is always fetched. Most instructions will use the next byte, so this technique considerably speeds throughput) Next, the operation of each opcode will follow the flowchart. !VMA is an indication of $FFFF on the address bus, R/!W = 1 and BS = 0. The following examples illustrate the use of the chart.

Example 1: LBSR (Branch Taken) Before Execution SP = F000

CYCLE-BY-CYCLE FLOW

Example 2: DEC (Extended)

CYCLE-BY-CYCLE FLOW

* The data bus has the data at that particular address.

INSTRUCTION SET TABLES

The instructions of the MC6809E have been broken down into five different categories. They are as follows:

• 8-bit operation (Table 4)
• 15-bit operation (Table 5)
• Index register/stack pointer instructions (Table 8)
• Relative branches (long or short) (Table 7)
• Miscellaneous instructions (Table 8)

Hexedecimal values for the instructions are given in Table 9.

PROGRAMMING AID

Figure 18 contains a compilation of data that will assist you in programming the MC6809E.

FIGURE 17 - CYCLE-BY-CYCLE PERFORMANCE (Sheet 1 of 5)

Notes

1. Each state shows

   Data bus	Offset High
   Address bus	NNN+ 1 (2)

2. Address NNNN is a location of opcode
3. If opcode is a two-byte opcode subsequent addresses are in parentheses (-).
4. Two-byte opcodes are highlighted.

FIGURE 17 - CYCLE-BY-CYCLE PERFORMANCE (Sheet 2 of 5)
FIGURE 17 - CYCLE-BY-CYCLE PERFORMANCE (Sheet 3 of 5)
FIGURE 17 - CYCLE-BY-CYCLE PERFORMANCE (Sheet 4 of 5)
FIGURE 17 - CYCLE-BY-CYCLE PERFORMANCE (Sheet 5 of 5)