The instruction set of the MC6809E is similar to that of the
MC6800 and is upward compatible at the source code level. The
number of opcodes has been reduced from 72 to 59, but because of
the expanded architecture and additional addressing modes, the
number of available opcodes (with different addressing modes) has
risen from 197 to 1464.
Some of the new instructions are described in detail below.
The push instructions have the capability of pushing onto either the hardware stack (S) or user stack (U) any single register or set of registers with a single instruction.
The pull instructions have the same capability of the push instruction, in reverse order. The byte immediately following the push or pull opcode determines which register or registers are to be pushed or pulled. The actual push/pull sequence is fixed; each bit defines a unique register to push or pull, as shown below.
Within the MC6809E, any register may be transferred to or
exchanged with another of like size; i.e. 8-bit to 8-bit or
16-bit to 16-bit.
Bits 4-7 of postbyte define the source register, while bits 0-3 represent the destination register. These are denoted as follows:
All other combinations are undefined and INVALID
The LEA (Load Effective Address) works by calculating the effective address used in an indexed instruction and stores that address value, rather than the data at that address, in a pointer register. This makes all the features of the internal addressing hardware available to the programmer. Some of the implications of this instruction are illustrated in Table 3
The LEA instruction also allows the user to access data and tables in a position independent manner. For example:
LEAX MSG1, PCR LBSR PDATA (Print message routine) MSG1 FCC 'MESSAGE'
This sample program prints 'MESSAGE'. By writing MSG1, PCR, the assembler computes the distance between the present address and MSG1. This result is placed as a constant into the LEAX instruction which will be indexed from the PC value at the time of execution. No matter where the code is located when it is executed, the computed offset from the PC will put the absolute address of MSG1 into the X pointer register. This code is totally position-independent.
The LEA instructions are very powerful and use an internal holding register (temp). Care must be exercised when using the LEA instructions with the auto increment and auto decrement addressing modes due to the sequence of internal operations. The LEA internal sequence is outlined as follows:
LEAa,b+ (any of the 18 bit pointer registers X, Y, U, or S may be substituted for a and b.)1. b => temp (calculate the EA) 2. b+1 => b (modify b, postincrement) 3. temp => a (load a)LEAa, - b1. b-1 => temp (calculate EA with predecrement) 2. b-1 => b (modify b, predecrement) 3. temp => a (load a)
TABLE 3 - LEA EXAMPLES
|LEAX 10,X||X + 10 => X||Adds 5-Bit Constant 10 to X|
|LEAX 500,X||X + 500 => X||Adds 15-Bit Constant 500 to X|
|LEAY A,Y||Y + A => Y||Adds 8-Bit A Accumulator to Y|
|LEAY D,Y||Y + D => Y||Adds 16-Bit D Accumulator to Y|
|LEAU -10,U||U - 10 => U||Subtracts 10 from U|
|LEAS -10,S||S - 10 => S||Used to Reserve Area on Stack|
|LEAS 10,S||S + 10 => S||Used to 'Clean Up' Stack|
|LEAX 5,S||S + 5 => S||Transfers As Well As Adds|
Auto increment-by-two and auto decrement-by-two instructions work similarly. Note that LEAX,X+ does not change X; however LEAX, - X does decrement X. LEAX 1,X should be used to increment X by one.
Multiplies the unsigned binary numbers in the A and B accumulator and places the unsigned result into the 16-bit D accumulator. This unsigned multiply also allows multiple-precision muitiplications.
The MC6809E has the capability of program-counter relative branching throughout the entire memory map. In this mode, if the branch is to be taken, the 8- or 16-bit signed offset is added to the value of the program counter to be used as the effective address. This allows the program to branch anywhere in the 64K memory map. Position independent code can be easily generated through the use of relative branching. Both short (8 bit) and long (16 bit) branches are available
After encountering a sync instruction, the MPU enters a sync state, stops processing instructions, and waits for an interrupt. If the pending interrupt is non-maskable (!NMI) l or maskable (!FIRQ, !IRQ) with its mask bit (F or l) clear, the processor will cear the sync state and perform the normal interrupt stacking and service routine. Since !FIRQ and !IRQ are not edge triggered, a low level with a minimum duration of three bus cydes is required to assure that the interrupt will be taken. If the pending interrupt is maskable (!FIRQ, !IRQ) with its mask bit (F or I) set, the processor will clear the sync state and continue processing by executing the next in-line instruction. Figure 16 depicts sync timing.
A software interrupt is an instruction which will cause an interrupt and its associated vector fetch. These software interrupts are useful in operating system calls, software debugging, trace operations, memory mapping, and software development systems. Three levels of SWI are available on the MC6809E and are prioritized in the following order: SWI, SWI2, SWI3.
The MC6809 has the capability of processing 16-bit data. Thee instructions include loads. stores, compares, adds, subtracts, transfers. exchanges, pushes, and pulls.
The address-bus cycle-by-cycle performance chart (Figure 16) illustrates the memory-access sequence corresponding to each possible instruction and addressing mode in the MC6809E. Each instruction begins with an opcode fetch. While that opcode is being internally decoded. the next program byte is always fetched. Most instructions will use the next byte, so this technique considerably speeds throughput) Next, the operation of each opcode will follow the flowchart. !VMA is an indication of $FFFF on the address bus, R/!W = 1 and BS = 0. The following examples illustrate the use of the chart.
Example 1: LBSR (Branch Taken) Before Execution SP = F000
|2||8001||20||1||Offset high byte|
|3||8002||00||1||Offset low byte|
|6||A000||*||1||Computed branch address|
|8||EFFE||80||0||Stack high order byte of return address|
|9||EFFE||03||0||Stack low order byte of return address|
Example 2: DEC (Extended)
|2||8001||A0||1||Operand address, high byte|
|3||8002||00||1||Operand address, low byte|
|5||A000||80||1||Read the data|
|7||EFFE||7F||0||Store the decremented data|
* The data bus has the data at that particular address.
The instructions of the MC6809E have been broken down into five different categories. They are as follows:
Hexedecimal values for the instructions are given in Table 9.
Figure 18 contains a compilation of data that will assist you in programming the MC6809E.
FIGURE 17 - CYCLE-BY-CYCLE PERFORMANCE (Sheet 1 of 5)
|Data bus||Offset High|
|Address bus||NNN+ 1 (2)|
FIGURE 17 - CYCLE-BY-CYCLE
PERFORMANCE (Sheet 2 of 5)
FIGURE 17 - CYCLE-BY-CYCLE PERFORMANCE (Sheet 3 of 5)
FIGURE 17 - CYCLE-BY-CYCLE PERFORMANCE (Sheet 4 of 5)
FIGURE 17 - CYCLE-BY-CYCLE PERFORMANCE (Sheet 5 of 5)